The present invention relates to a method and apparatus providing reconfigurable pipelined digital processing for use in massively parallel multi-processing systems. When pipelined calculations are to be performed, it is often necessary to delay one partial result by some amount of time before combining it with another partial result. Thus, for example, in the calculation EQU (a.sub.1 .times.b.sub.1)+c.sub.1
the c.sub.1 value must be delayed during the computations a.sub.1 .times.b.sub.1. As shown schematically in FIG. 1, a.sub.1, b.sub.1, and c.sub.1 are results of a previous part of the pipeline, and the three operands are supplied as inputs to registers 1, 2, and 3, respectively, on every clock pulse. The operands a.sub.1 and b.sub.1 are multiplied in a multiplier 2 with the result being stored in register 4. In the meantime, c.sub.1 is held or delayed in register 5 during multiplication of a.sub.1 .times.b.sub.1. The product of a.sub.1 .times.b.sub.1 is added to c.sub.1 in an adder 4 and the sum is stored in register 6. FIG. 2 is a table showing the contents of each register for clocks pulses T.sub.1 -T.sub.8.
In the design of a pipeline, it is important that there be proper connections between registers and arithmetic functional units, and that there be proper timing alignment of data for processing. The reconfigurable pipelined processor of the present invention provides both of these features.